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java.lang.Objectcom.sun.electric.tool.io.output.Output
com.sun.electric.tool.io.output.Topology
com.sun.electric.tool.io.output.Verilog
public class Verilog
This is the Simulation Interface tool.
Nested Class Summary |
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Nested classes/interfaces inherited from class com.sun.electric.tool.io.output.Topology |
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Topology.CellAggregateSignal, Topology.CellNetInfo, Topology.CellSignal, Topology.MyCellInfo, Topology.Visitor |
Nested classes/interfaces inherited from class com.sun.electric.tool.io.output.Output |
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Output.OutputCellInfo, Output.WriteJELIB |
Field Summary | |
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static Variable.Key |
VERILOG_BEHAVE_FILE_KEY
key of Variable holding file name with Verilog. |
static Variable.Key |
VERILOG_CODE_KEY
key of Variable holding verilog code. |
static Variable.Key |
VERILOG_DECLARATION_KEY
key of Variable holding verilog declarations. |
static Variable.Key |
VERILOG_DEFPARAM_KEY
key of Variable holding verilog defparams. |
static Variable.Key |
VERILOG_EXTERNAL_CODE_KEY
key of Variable holding verilog code that is external to the module. |
static Variable.Key |
VERILOG_PARAMETER_KEY
key of Variable holding verilog parameters. |
static Variable.Key |
VERILOG_TEMPLATE_KEY
key of Variable holding verilog templates. |
static Variable.Key |
WIRE_TYPE_KEY
key of Variable holding verilog wire time. |
Fields inherited from class com.sun.electric.tool.io.output.Topology |
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topCell |
Fields inherited from class com.sun.electric.tool.io.output.Output |
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dataOutputStream, printWriter, quiet, stringWriter |
Method Summary | |
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protected boolean |
canParameterizeNames()
Method to tell whether the topological analysis should mangle cell names that are parameterized. |
protected void |
done()
Abstract method called after traversal |
static Cell |
findCell(java.lang.String verilogName,
View preferredView)
Find a cell corresponding to the Verilog-style name of a cell. |
protected java.lang.String |
getGlobalName(Global glob)
Method to return the proper name of a Global signal |
protected java.lang.String |
getGroundName(Network net)
Method to return the proper name of Ground |
protected java.lang.String |
getPowerName(Network net)
Method to return the proper name of Power |
protected java.lang.String |
getSafeCellName(java.lang.String name)
Method to adjust a cell name to be safe for Verilog output. |
protected java.lang.String |
getSafeNetName(java.lang.String name,
boolean bus)
Method to adjust a network name to be safe for Verilog output. |
protected Netlist.ShortResistors |
getShortResistors()
Tell the Hierarchy enumerator how to short resistors |
static java.lang.String |
getVerilogSafeName(java.lang.String name,
boolean isNode,
boolean isBus)
|
protected boolean |
isAggregateNameGapsSupported()
Abstract method to decide whether aggregate names (busses) can have gaps in their ranges. |
protected boolean |
isAggregateNamesSupported()
Method to report that aggregate names (busses) ARE used. |
protected boolean |
isCaseSensitive()
Abstract method to decide whether netlister is case-sensitive (Verilog) or not (Spice). |
protected boolean |
isLibraryNameAlwaysAddedToCellName()
Method to report that library names ARE always prepended to cell names. |
protected boolean |
isNetworksUseExportedNames()
Method to report that export names DO take precedence over arc names when determining the name of the network. |
protected boolean |
isSeparateInputAndOutput()
Method to report whether input and output names are separated. |
protected boolean |
skipCellAndSubcells(Cell cell)
If the netlister has requirments not to netlist certain cells and their subcells, override this method. |
protected void |
start()
Abstract method called before hierarchy traversal |
protected void |
writeCellTopology(Cell cell,
Topology.CellNetInfo cni,
VarContext context,
Topology.MyCellInfo info)
Method to write cellGeom |
static void |
writeVerilogFile(Cell cell,
VarContext context,
java.lang.String filePath)
The main entry point for Verilog deck writing. |
Methods inherited from class com.sun.electric.tool.io.output.Topology |
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enterCell, enumerateLayoutView, getCellNetInfo, getUniqueCellName, isChooseBestExportName, isShortExplicitResistors, isShortResistors, maxNameLength, parameterizedName, unIndexedName, validateSkippedCell, writeCell, writeCell |
Methods inherited from class com.sun.electric.tool.io.output.Output |
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closeBinaryOutputStream, closeStringsOutputStream, closeTextOutputStream, emitCopyright, exportCellCommand, getAreaToPrint, openBinaryOutputStream, openStringsOutputStream, openTextOutputStream, saveJelib, setContinuationString, setOutputWidth, writeCell, writeLibrary, writePanicSnapshot, writeWidthLimited |
Methods inherited from class java.lang.Object |
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clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait |
Field Detail |
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public static final Variable.Key VERILOG_CODE_KEY
public static final Variable.Key VERILOG_DECLARATION_KEY
public static final Variable.Key VERILOG_PARAMETER_KEY
public static final Variable.Key VERILOG_EXTERNAL_CODE_KEY
public static final Variable.Key WIRE_TYPE_KEY
public static final Variable.Key VERILOG_TEMPLATE_KEY
public static final Variable.Key VERILOG_DEFPARAM_KEY
public static final Variable.Key VERILOG_BEHAVE_FILE_KEY
Method Detail |
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public static java.lang.String getVerilogSafeName(java.lang.String name, boolean isNode, boolean isBus)
public static void writeVerilogFile(Cell cell, VarContext context, java.lang.String filePath)
cell
- the top-level cell to write.context
- the hierarchical context to the cell.filePath
- the disk file to create.protected void start()
Topology
start
in class Topology
protected void done()
Topology
done
in class Topology
protected boolean skipCellAndSubcells(Cell cell)
Topology
skipCellAndSubcells
in class Topology
protected void writeCellTopology(Cell cell, Topology.CellNetInfo cni, VarContext context, Topology.MyCellInfo info)
writeCellTopology
in class Topology
protected java.lang.String getSafeCellName(java.lang.String name)
getSafeCellName
in class Topology
name
- the cell name.
protected java.lang.String getPowerName(Network net)
getPowerName
in class Topology
protected java.lang.String getGroundName(Network net)
getGroundName
in class Topology
protected java.lang.String getGlobalName(Global glob)
getGlobalName
in class Topology
protected boolean isNetworksUseExportedNames()
isNetworksUseExportedNames
in class Topology
protected boolean isLibraryNameAlwaysAddedToCellName()
isLibraryNameAlwaysAddedToCellName
in class Topology
protected boolean isAggregateNamesSupported()
isAggregateNamesSupported
in class Topology
protected boolean isAggregateNameGapsSupported()
isAggregateNameGapsSupported
in class Topology
protected boolean isSeparateInputAndOutput()
isSeparateInputAndOutput
in class Topology
protected boolean isCaseSensitive()
isCaseSensitive
in class Topology
protected java.lang.String getSafeNetName(java.lang.String name, boolean bus)
getSafeNetName
in class Topology
bus
- true if this is a bus name.protected Netlist.ShortResistors getShortResistors()
getShortResistors
in class Topology
protected boolean canParameterizeNames()
canParameterizeNames
in class Topology
public static Cell findCell(java.lang.String verilogName, View preferredView)
getVerilogName(com.sun.electric.database.hierarchy.Cell)
.
verilogName
- the Verilog-style name of the cellpreferredView
- the preferred cell view. Schematic if null.
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